Memory word drive system for noise reduction



Aug. 11, 1970 R. MOSENKIS 3,524,175

MEMORY WORD DRIVE SYSTEM FOR NOISE REDUCTION Filed April 4, 1968 INVENTOR ROBERT MUSE/W05 ATTORNEY United States. Patent 3,524,175 MEMORY WORD DRIVE SYSTEM FOR NOISE REDUCTION Robert Mosenkis, Philadelphia, Pa., assignor to Sperry Rand Corporation, New York, N.Y., a corporation of Delaware Filed Apr. 4, 1968, Ser. No. 718,783

Int. Cl. Gllc 7/02 US. Cl. 340-174 Claims ABSTRACT OF THE DISCLOSURE The invention relates to an arrangement for minimizing noise coupled into a wire memory from unselected word lines. Small currents produced in these unselected lines when the desired line is energized induces opposite polarity noise signals in the wire memory so that they are effectively cancelled.

BACKGROUND. OF THE INVENTION This invention relates in general to memory devices and in particular, relates to noise reduction techniques in thin film memory devices.

Known prior art techniques such as disclosed in U.S. 3,315,241 and US. 3,223,986 for eliminating noise in thin film memory devices utilize a two magnetic element per bit construction whereas the instant invention requires only one memory per bit. This aspect simplifies construction and provides better packing density.

SUMMARY OF THE INVENTION This invention relates to an arrangement of the matrixing transformers connected to the drive lines of a thin film wire memory device so as to minimize noise coupled to the wire. The transformers that are connected to adjacent drive lines are phase so that the currents produced in unselected drive lines couple opposite voltages into the wire memory and thereby effectively cancel each other. This is particularly useful in mass memories on the order of a million bits or more which utilize long drive lines.

Accordingly, it is an object of this invention to provide a new and improved drive arrangement for use with a thin film memory device.

It is a further object of this invention to provide a new and improved memory drive arrangement for use in a mass memory on the order of a million hits or more.

BRIEF DESCRIPTION OF THE DRAWING In the drawing there is depicted a circuit schematic of the memory word drive arrangement for the instant invention.

DESCRIPTION OF THE PREFERRED EMBODIMENT Referring now in greater detail to the drawing, there is depicted the memory arrangement comprising the word drive lines 11, 13, and 17 which are shown as resistance elements and the plated wire sections 10, 12, 14 and 16. In actual practice, the plated wire sections comprise one continuous plated wire but are shown in sections for ease of understanding. It should be understood that in an actual embodiment, there would be a plurality of such word lines. The plated Wire memory in one embodiment comprises a 5 mil beryllium-copper substrate upon which is coated a permalloy film on the order of 10,000 A. thick. The permalloy film comprises approximately an 80% nickel and 20% iron composition. The magnetic film is deposited on the wire substrate with the property of uniaxial anisotropy so that it has an EASY axis which is circumferential and a HARD axis which is longitudinal to "ice the length of the wire. In an actual mass memory arrangement the plated wires 10, 12, 14 and 16 would have an actual length of approximately 8. feet and are held in position in a plastic carrier (not shown). The drive lines 11, 13, 15 and 17 which are positioned orthogonally to the plated wire and which are approximately 6 feet in length comprise .032 inch wide copper lines on .045 inch centers. These lines are bonded to a substrate (not shown) which in turn are bonded to the plastic carrier in a manner such that the wires and drive lines are juxtaposed to one another. The intersection of the plated wire sections 10, 12, 14 and 16 with a respective drive line 11, 13, 15 and 17 comprises a bit position whereat binary information is stored. 'It should be understood that in actual practice, a single word line such as 11 would have a plurality of wires such as 10 positioned along its length in order to store a plurality of information bits.

The word lines 11, 13, 15 and 17 in the mass memory arrangement are driven by the respective transformers T11, T21, T31 and Tnl having a 1:1 transformer ratio. It should be noted that adjacent transformers T11, T21, etc. are each phased opposite from one another. This .phasin-g is indicated by the dot placement near the primary and secondary windings of the transformers. The dot convention indicates the direction of the current in the secondary winding with respect to the current direction in the primary Winding. This will be discussed in greater detail hereinafter.

Each of the primary windings of transformers T11, T21, T31 and Tnl is connected through respective diodes 18, 20, 22 and 24 to the NPN transistors QA1, QA2, QA3 and QAn. These transistors comprise what is known in the art as A-switches. Connected to the other side of the primaries of the transformers is the NPN transistor QB1. The transistor QBl is referred to conventionally as a B-switch.

Reading and writing in the instant inventions occurs on the trailing edge of the signal applied to the respective word line 11, 13, 15 and 17. In order to select a particular word line in the memory to perform a read or Write cycle it is required to energize an A-switch and a B- switch. Accordingly, let us assume that it is required to energize the word line 11 and to read the binary information stored along its length during a read cycle. The B- switch QBl is first energized by the application of the positive pulse 6 and then the A-switch, QA1, is energized. Thus, the transistor QA1 is forward-biased by the positive pulse 8 applied to its base electrode and the transistor QBl is forward-biased by the positive pulse 6 applied to its base electrode. Current therefore flows from B+ (which is in reality a pulsed current source in order to provide a single circuit for regulating the word current amplitude and waveform) through the collector and emitter junctions of transistor QA1, the diode 18, the primary winding of T11, the collector and emitter junctions of transistor QBl to ground. After the above current flow is established, the B-switch is turned off. Current flows through the diode 18 since it is forward-biased caused by its anode being slightly below B+ and its cathode being slightly above ground.-

Since the transformer dot convention requires that the current into the dot near the primary winding must have current flowing out of the dot in the secondary winding, the direction of the current I1 induced in the transformer secondary is in the direction shown. As is well known in the art, the current flowing through the word line juxtaposed to a plated wire causes the magnetization vectors oriented alon the EASY axis to be rotated to some angle less than the HARD axis. The current in the word line 11 causes a signal to be induced in the plated wire section 10 whose polarity is indicative of whether a binary 1 or 0 is stored thereat. This signal is sensed across ends of the plated wire and is detected by a sense amplifier (not shown).

Due to wiring inductance from the bottom of the primary winding of transformer T11 to ground through the B-switch QB1, a negative spike is produced at the common tie point of the transformer primaries during the trailing edge of the word current. This negative pulse is caused by the fact that during the time period when the Word current is being turned off (i.e., during the trailing edge) the wiring inductance develops a negative pulse which opposes this reduction of current.

The negative signal which is developed at the common primary winding tie point by the highly inductive load is applied to the cathode elements of diodes 24 22 and 24 via the primary windings of transformers T21, T31 and Tn1. The anodes of diodes 20, 22 and 24 are approximately ground potential since they are connected through the resistors to ground potential. Hence, since the anodes are positive with respect to the cathodes the diodes 22 and 24 become forward-biased. This causes the currents 12, I3 and 14 to flow from ground at one end of the resistors to the negative potential at the collector of the transistor QB1. In other words, the negative pulse developed at the transformer tie point causes transistor QB1 to become a negative voltage source. The currents 12, I3 and I4 complete the circuit by returning to ground potential via the ground terminal connected to the emitter of transistor QB1.

It should be noted that the collector of transistor QB1 when it is selected is slightly positive with respect to ground and therefore there is a slight back-biasing on diodes 20, 22 and 24. Even if the negative spike were not sufiicient to forward bias them, their capacitance (which is an inverse function of the back bias voltage) will allow the currents 12, I3 and I4.

The currents I2, 13 and 14 through the primary windings of transformers T21, T31 and Tnl induce the currents 12, I3 and 14' to flow in the respective transformer secondaries. It should be noted that because of the particular winding arrangement of the secondary with respect to the primary windings of the transformers T21, T31 and T111 as represented by the dot convention, the currents in the secondaries flow oppositely in adjacent word lines 13, 15 and 17. These currents charge up the distributed capacitance between the plated wires 12, 14 and 16 and the respective drive lines 13, 15 and 17. Since the currents which charge up the distributed capacitance flow oppositely in adjacent unenergized word lines, it causes opposite voltage (i.e., the voltage coupled into wire 12 is opposite from that coupled into 14) to be coupled along the plated wire. These opposite polarity voltages which may be considered as noise signal effectively cancel one another and therefore the noise signals coupled to the wire is minimized or virtually eliminated.

It therefore can be readily seen that by alternating the phasing of adjacent transformers, the noise on adjacent word lines is equal and opposite thus providing cancellation thereof on the plated wires during the energizing of a single drive line 11. It should be apparent that the above noise cancelling technique applies during the application of the other drive lines 13, 15 or 17.

The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows:

1. A memory word drive arrangement comprising:

(a) a plurality of memory word lines, each different one being juxtaposed to a memory cell which stores binary information;

(b) a plurality of transformer means each having a primary and secondary wherein each different secondary is connected across a diiferent word line; the primary of each different transformer being connected to energizing means;

(c) the transformers connected to adjacent word lines being poled oppositely.

2. The memory word drive arrangement in accordance with claim 1 wherein said memory cell comprises a storage position along a plated magnetizable wire.

3. The memory word drive arrangement in accordance with claim 1 wherein said transformer has a 1:1 turns ratio.

4. The memory word drive arrangement in accordance with claim 2 wherein said magnetizable wire comprises a substrate upon which is coated a permalloy film whose proportions are approximately nickel and 20% iron.

5. The memory Word drive arrangement in accordance with claim 2 wherein said permalloy coating has the property of uniaxial anisotropy.

References Cited 3,343,127 9/1967 Rufi 340174 X 3,419,856 12/1968 Doughty 340-174 3,422,409 1/ 1969 Bartik 340174 OTHER REFERENCES IBM Technical Disclosure Bulletin, Memory Drive System by Coricari et 211., vol. 9, No. 7, December 1966, pp. 928-929.

STANLEY M. URYNOWICZ, JR., Primary Examiner 

